The present invention relates to a semiconductor device and is favorably used to a semiconductor device including an analog to digital converter, for example.
When an AD (Analog to Digital) converter is used for uses that require functional safety, it has been requested to perform fault detection on the AD converter so as to validate conversion data. It has also been requested to perform the fault detection on a digital sigma AD converter that is used for highly precise measurement use.
Japanese Unexamined Patent Application Publication No. 2007-300469 discloses fault detection on an AD conversion device using signals output from a sampling amplifier, which is a circuit disposed in a preceding stage of a comparison unit, in a comparison period in which the comparison unit is executing AD conversion, where a cycle of the AD conversion is divided into an initialization period, a sampling period, and the comparison period. The initialization period indicates a period from a start timing of the AD conversion to an initialization end timing. The sampling period indicates a period from the initialization end timing to a sampling end timing. The comparison period indicates a period from the sampling end timing to the start timing of a next AD conversion process.
Japanese Unexamined Patent Application Publication No. 2003-177161 discloses a configuration of a test device that includes a signal processing unit for converting a signal added with a dither signal into a digital signal and evaluates normality of an electronic device by comparing the digital signal output from the signal processing unit with an expected value. The dither signal is used to reduce quantization error in AD conversion.
Japanese Unexamined Patent Application Publication No. 2008-252520 discloses a configuration of a dither generation circuit that generates a plurality of square waves each with different frequencies.